SH7708 Datasheet, PDF (81/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

MMUCR
31
0
Index
9
0
SV 0 0 RC 0 TF IX AT
Way selection
PTEH register
31
17
VPN
12 10 8
0
VPN 0 ASID
PTEL register
31
10
0
PPN
0 V 0 PR SZ C D SH 0
Write
Way 0 to 3
Write
0 VPN(31–17) VPN(11–10) ASID(7–0) V PPN(31–10) PR(1–0) SZ C D SH
31
Address array
Data array
Figure 3.9 Operation of LDTLB Instruction
3 . 4 . 4 Avoiding Synonym Problems
When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of
virtual addresses are mapped onto a single physical address, the same physical address data will be
recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The
reason why this problem only occurs when using a 1-kbyte page is explained below with reference
to figure 3.10.
To achieve high-speed operation of the SH7708 Series cache, an index number is created using
virtual address bits 10–4. When a 4-kbyte page is used, virtual address bits 10–4 are included in the
offset, and since they are not subject to address translation, they are the same as physical address
bits 10–4. In cache-based address comparison and recording in the address array, since the cache tag
address is a physical address, physical address bits 31–10 are recorded.
When a 1-kbyte page is used, also, a cache index number is created using virtual address bits 10-4.
However, in the case of a 1-kbyte page, virtual address bit 10 is subject to address translation and
therefore may not be the same as physical address bit 10. Consequently, the physical address is
recorded in a different entry from that of the index number indicated by the physical address in the
cache address array.
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