SH7708 Datasheet, PDF (518/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 17.7 Bus Timing (Conditions: Clock Mode 0/1/2/7, V_CC = 3.15–3.6 V, Ta = –20 to
75°C) (cont)
–60*¹
Item
Symbol
Min
Max
Unit Figure
RAS delay time 1
t_RASD1
—
13
ns
17.23–17.44
RAS delay time 2
t_RASD2
1.5
13
ns
CAS delay time 1
t_CASD1
—
13
ns
CAS delay time 2
t_CASD2
1.5
13
ns
DQM delay time
t_DQMD
1.5
12
ns
CKE delay time
t_CKED
—
12
ns
CE delay time
t_CED
—
13
ns
17.45–17.51
OE, RFSH delay time
t_OED
—
13
ns
ICIORD delay time
t_ICRSD
—
12
ns
17.56–17.58
ICIOWR delay time
t_ICWSD
—
12
ns
IOIS16 setup time
t_IO16S
12
—
ns
IOIS16 hold time
t_IO16H
4
—
ns
Notes 1. Upper limit of external bus clock is 60 MHz.
2. WAIT is a synchronous signal. Operation cannot be guaranteed if the setup and hold
times shown here are not observed.
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