SH7708 Datasheet, PDF (416/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

1. Setting the serial mode register (SCSMR): Set the O/E bit to 0 when the IC card uses the
direct convention or to 1 when it uses the inverse convention. Select the on-chip baud rate
generator clock source with the CKS1 and CKS0 bits (see section 14.3.5, Clock). When
bit 7 (C/A) of the serial mode register (SCSMR) is set to 1 (default value : 1), bit 2
(TEND) of the serial status register (SCSSR) is simply set to 1 (TXI interrupt request) 1
etu (default value : 2.5 etu) after transmission of a 1-byte character, and 11 etu continuous
transmission (block transfer protocol) cannot be performed.
2. Setting the bit rate register (SCBRR): Set the bit rate. See section 14.3.5, Clock, to see
how to calculate the set value.
3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as
they do for the ordinary SCI. See section 13, Serial Communication Interface, for more
information. The CKE0 bit specifies the clock output. When no clock is output, set 0;
when a clock is output, set 1.
4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to
0 for IC cards that use the direct convention and both to 1 when the inverse convention is
used. The SMIF bit is set to 1 for the smart card interface.
Figure 14.4 shows sample waveforms for register settings of the two types of IC cards (direct
convention and inverse convention) and their start characters.
In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and
communication is LSB first. The start character data is H'3B. The parity bit is even (from the
smart card standards), and thus a 1.
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z,
and communication is MSB first. The start character data is H'3F. The parity bit is even (from
the smart card standards), and thus a 0, which corresponds to state Z.
Only data bits D7–D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in
SCSMR to odd parity mode. This applies to both transmission and reception.
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