SH7708 Datasheet, PDF (173/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Clock pulse generator
CAP1
CKIO
Cycle = Bcyc
CAP2
XTAL
EXTAL
Crystal
oscillator
PLL circuit 1
(× 1, 2, 3,4)
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
× 1/4
Divider 2
×1
× 1/2
× 1/3
× 1/4
CPG control unit
MD2
MD1
MD0
Clock frequency
control circuit
FRQCR
Standby control
circuit
STBCR
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
Standby
control
Bus interface
Internal bus
FRQCR: Frequency control register
Figure 9.2 Block Diagram of Clock Pulse Generator(SH7708R)
The clock pulse generator blocks function as follows:
1. PLL Circuit 1: PLL circuit 1 doubles, triples*, quadruples, or leaves unchanged the input clock
frequency from the CKIO terminal. The multiplication rate is set by the frequency control
register. When this is done, the phase of the leading edge of the internal clock is controlled so
that it will agree with the phase of the leading edge of the CKIO pin.
Note: SH7708R only
2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal
oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio
159