SH7708 Datasheet, PDF (125/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 6.3 IRL3–IRL0 Pins and Interrupt Levels
IRL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IRL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IRL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IRL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Priority LevelInterrupt Request
15
Level 15 interrupt request
14
Level 14 interrupt request
13
Level 13 interrupt request
12
Level 12 interrupt request
11
Level 11 interrupt request
10
Level 10 interrupt request
9
Level 9 interrupt request
8
Level 8 interrupt request
7
Level 7 interrupt request
6
Level 6 interrupt request
5
Level 5 interrupt request
4
Level 4 interrupt request
3
Level 3 interrupt request
2
Level 2 interrupt request
1
Level 1 interrupt request
0
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no
transient level on the IRL pin change is detected. In standby mode, as the peripheral clock is
stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead.
Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed
in standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt handling starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by IRL interrupt
handling.
111