SH7708 Datasheet, PDF (89/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

3 . 5 . 5 Processing Flow in Event of MMU Exception (Same Processing Flow
for Address Error)
Figure 3.12 shows the MMU exception signals in instruction fetch mode.
IF ID EX MA WB
ID EX MA WB
ID EX MA WB
NOP
NOP
MMU exception handler
IF ID
Handler transition
processing
EX MA WB
: Exception source stage
IF = Instruction fetch
ID = Instruction decode
EX = Instruction execution
MA = Memory access
WB = Write back
NOP = No operation
Figure 3.12 MMU Exception Signals in Instruction Fetch
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