SH7708 Datasheet, PDF (246/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

When synchronous DRAM is connected, the RAS signal, CAS signal, RD/WR signal, and byte
control signals DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses
multiplexed. Control of RAS, CAS, data timing, and address multiplexing is set with MCR.
When DRAM is connected, the RAS2 signal, CAS2H signal, CAS2L signal, and RD/WR signal
are all asserted and addresses multiplexed. Control of RAS2, CAS, data timing, and address
multiplexing is set with DCR.
Area 3: Area 3 physical address bits A28–A26 are 011. Address bits A31–A29 are ignored and the
address range is H'0C000000 + H'20000000 × n – H'0FFFFFFF + H'20000000 × n (n = 0–6, n =
1–6 is the shadow space).
Normal memories like SRAM and ROM, as well as DRAM, pseudo-SRAM, and synchronous
DRAM, can be connected to this space. Byte, word or longword can be selected as the bus width
using the A3SZ1–A3SZ0 bits in BCR2 for normal memory. For DRAM and pseudo-SRAM,
word or longword can be selected using the SZ bit in MCR. When synchronous DRAM is
connected, set to longword using the SZ bit in MCR.
When area 3 space is accessed, CS3 is asserted.
When normal memories are connected, the RD signal that can be used as OE and the WE0–WE3
signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait
cycles using the A3W1–A3W0 bits in WCR2. When normal memory is connected, only, any
number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT).
When synchronous DRAM is connected, the RAS signal, CAS signal, RD/WR signal, and byte
control signals DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses
multiplexed. When DRAM is connected, the RAS signal, CASHH signal, CASHL signal,
CASLH signal, CASLL signal, and RD/WR signal are all asserted and addresses multiplexed.
When pseudo-SRAM is connected, the CE signal, OE/RFSH signal, and WE0 , WE1 , WE2, and
WE3 signals are asserted. For all of these, control of RAS , CAS , and data timing and of address
multiplexing is set with MCR.
Area 4: Area 4 physical address bits A28–A26 are 100. Address bits A31–A29 are ignored and
the address range is H'10000000 + H'20000000 × n – H'13FFFFFF + H'20000000 × n (n = 0–6,
n = 1–6 is the shadow space).
Only normal memories like SRAM and ROM can be connected to this space. Byte, word, or
longword can be selected as the bus width using the A4SZ1–A4SZ0 bits in BCR2. When the area
4 space is accessed, the CS4 signal is asserted. The RD signal that can be used as OE and the
WE0–WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A4W2–A4W0 bits in WCR2. Also, any number of waits
can be inserted in each bus cycle by means of the external wait pin (WAIT).
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