SH7708 Datasheet, PDF (259/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Wait State Control: As the clock frequency increases, it becomes impossible to complete all
states in one cycle as in basic access. Therefore, provision is made for state extension by using the
setting bits in WCR2, MCR, and DCR. The timing with state extension using these settings is
shown in figure 10.15. Up to four additional Tpc cycles (cycles used to secure the RAS precharge
time) can be inserted by means of the TPC bits in MCR and DCR. However, if there is a DRAM
access request immediately after an auto-refresh (CAS-before-RAS refresh), the interval until the
next assertion of RAS is 2 cycles, regardless of the values in MCR and DCR. The number of
cycles from RAS assertion to CAS assertion can be set to between 1 and 4 by inserting Trw cycles
by means of the RCD bits in MCR and DCR. The number of cycles from CAS assertion to the
end of the access can be varied between 1 and 3 according to the setting of A1–2W (1,0) or A3W
(1,0) in WCR2.
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