SH7708 Datasheet, PDF (288/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Basic Timing: Figure 10.33 shows the basic timing for pseudo-SRAM. Tpc is the precharge
cycle, and Tr is the CE assert cycle. Tc1 is the write data cycle, BS the assert cycle, and Tc2 the
read data latch cycle.
CKIO
Tr
Tc1
Tc2
(Tpc)
A25 to A0
RD/WR
CE
OE/RFSH
(read)
D31 to D0
(read)
WEn
(write)
D31 to D0
(write)
BS
Figure 10.33 Basic Access Timing for Pseudo-SRAM
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