SH7708 Datasheet, PDF (82/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Virtual address 1 H'00000000 → physical address H'00000400
Virtual address 2 H'00000400 → physical address H'00000400
Virtual address 1 is recorded in cache entry H'00, and virtual address 2 in cache entry H'40. Since
the two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same
as a physical address already used in another TLB entry, it should be recorded in such a way that
physical address bit 10 is the same.
68