SH7708 Datasheet, PDF (230/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): These bits set the RAS–CAS delay time for
the DRAM connected to area 2.
Bit 13: RCD1 Bit 12: RCD0 Description
0
0
1 cycle
value)
1
2 cycles
1
0
3 cycles
1
4 cycles
(Initial
Bits 9 and 8—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): These bits set the
RAS assert period for CAS-before-RAS refreshing of the DRAM connected to area 2.
In the SH7708, set the same values in the TRAS bits in MCR and DCR.
Bit 9: TRAS1 Bit 8: TRAS0 Description
0
0
2 cycles
value)
1
3 cycles
1
0
4 cycles
1
5 cycles
(Initial
Bit 6—Burst Enable (BE): Specifies whether to conduct a burst access of the DRAM connected to
area 2.
Bit 6: BE
0
1
Description
Burst disabled
value)
High-speed page mode access
(Initial
Bits 4 and 3—Address Multiplex (AMX1, AMX0): These bits specify address multiplexing for the
DRAM connected to area 2.
Bit 4: AMX1
0
1
Bit 3: AMX0
0
1
0
1
Description
8-bit column address product
value)
9-bit column address product
10-bit column address product
11-bit column address product
(Initial
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