SH7708 Datasheet, PDF (266/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Refresh Timing: The bus state controller includes a function for controlling DRAM refreshing.
Refreshing using a CAS-before-RAS cycle can be performed by clearing the RMODE bit to 0 and
setting the RFSH bit to 1 in MCR for area 3 DRAM, or by clearing the RMODE bit to 0 and
setting the RFSH bit to 1 in DCR for area 2 DRAM. It also supports self-refresh mode.
When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals determined
by the input clock selected by bits CKS2–CKS0 in RTCSR, and the value set in RTCOR. The
value of bits CKS2–CKS0 in RTCOR should be set so as to satisfy the stipulation for the
DRAM refresh interval. First make the settings for RTCOR, RTCNT, and the RMODE and
RFSH bits in MCR, then make the CKS2–CKS0 setting. When the clock is selected by CKS2 to
CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly
compared with the RTCOR value, and if the two values are the same, a refresh request is generated
and the IRQOUT pin goes low. If the SH7708 Series’ external bus can be used, CAS-before-RAS
refreshing is performed, and if there is no other interrupt request the IRQOUT pin goes high. At
the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.19 shows the
operation of CAS-before-RAS refreshing.
RTCOR value
RTCNT
RTCNT cleared to 0 when
RTCNT = RTCOR
H'00000000
RTCSR.CKS(2–0) = 000 ≠ 000
CMF
External bus
CMF flag cleared by start of
refresh cycle
CAS-before-RAS refresh cycle
Figure 10.19 CAS-Before-RAS Refresh Operation
Time
252