SH7708 Datasheet, PDF (359/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 1: Bit 0:
CKE1 CKE0 Description
0
0
Asynchronous mode Internal clock, SCK pin used for input pin (input signal is
ignored)
(Initial
value)
Synchronous mode
Internal clock, SCK pin used for serial clock output
(Initial
value)
1
Asynchronous mode Internal clock, SCK pin used for clock output*¹
Synchronous mode Internal clock, SCK pin used for serial clock output
1
0
Asynchronous mode External clock, SCK pin used for clock input*²
Synchronous mode External clock, SCK pin used for serial clock input
1
Asynchronous mode External clock, SCK pin used for clock input*²
Synchronous mode External clock, SCK pin used for serial clock input
Notes: 1. The output clock frequency is the same as the bit rate.
2 The input clock frequency is 16 times the bit rate.
13.2.7 Serial Status Register (SCSSR)
The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate the SCI operating status.
The CPU can always read and write to SCSSR, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written.
SCSSR is initialized to H'84 by a reset and in standby or module standby mode.
Bit: 7
6
5
Bit name: TDRE RDRF ORER
Initial value: 1
0
0
R/W: R/(W)* R/(W)* R/(W)*
Note: Only 0 can be written, to clear the flag.
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from SCTDR into SCTSR and new serial transmit data can be written in SCTDR.
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