SH7708 Datasheet, PDF (320/625 Pages) Renesas Technology Corp – SuperH™ RISC engine

1 1 . 2 . 5 Timer Counters (TCNT)
The timer counters are 32-bit read/write registers. The TMU has three timer counters, one for each
channel.
TCNT counts down upon input of a clock. The clock input is selected using the TPSC2–TPSC0
bits in the timer control register (TCR).
When a TCNT count-down results in an underflow (H'00000000 → H'FFFFFFFF), the underflow
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
Because the internal bus for the SH7708 Series on-chip supporting modules is 16 bits wide, a time
lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT
counts sequentially, this time lag can create discrepancies between the data in the upper and lower
halves. To correct the discrepancy, a buffer register is connected to TCNT so that upper and lower
halves are not read separately. The entire 32-bit data in TCNT can thus be read at once.
TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset. In standby mode, when
the PLL1 multiplication factor is changed in clock mode 0, 1, 2, or 7, or when the MSTP2 bit is
set to 1 in STBCR, TCNT retains its contents when the input clock selected for the channel is an
external clock (TCLK) or the peripheral clock (Pø), and continues operating when the selected
clock is the on-chip RTC output clock (RTCCLK).
TCNT:
Bit: 31
30
29
28
27
26
25
24
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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