W90P710_05 Datasheet, PDF (97/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Cache Test Register 1 (CTEST1)
Cache Test Register that will be read back to provide the status of cache RAM BIST. Whether the BIST
is finish and all of bank of SRAM are tested successfully will be presented in this register.
Register
CTEST1
Address
0xFFF6_0004
R/W
Description
R Cache test register 1
Reset Value
0x0000_0000
31
30
FINISH
23
22
15
14
7
BFAIL7
6
BFAIL6
29
21
13
5
BFAIL5
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
BFAIL4 BFAIL3
26
18
10
2
BFAIL2
25
17
9
1
BFAIL1
24
16
8
0
BFAIL0
BITS
[31]
[30:8]
[7]
[6]
[5]
[4]
[3]
FINISH
RESERVED
BFAIL7
BFAIL6
BFAIL5
BFAIL4
BFAIL3
DESCRIPTION
BIST completed
This bit is “0” initially. When BIST mode enabled, this bit will be “1”
after BIST test completed. The values of BFAIL0-7 are valid only
after FINISH = 1.
-
BIST test fail for data cache tag ram way 1
If this bit equals to “1”, it indicates the data cache tag ram for way
1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache tag ram way 0
If this bit equals to “1”, it indicates the data cache tag ram for way
0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 1
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 1 is tested fail by BIST. “0” means the test is passed.
BIST test fail for instruction cache tag ram way 0
If this bit equals to “1”, it indicates the instruction cache tag ram for
way 0 is tested fail by BIST. “0” means the test is passed.
BIST test fail for data cache ram way 1
If this bit equals to “1”, it indicates the data cache ram for way 1 is
tested fail by BIST. “0” means the test is passed.
- 97 -
Publication Release Date: January 17, 2005
Revision A.2