W90P710_05 Datasheet, PDF (299/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
SLOT #
CMD ADDR
(slot 1)
CMD DATA
(slot 2)
PCM LEFT
(slot 3)
PCM RIGHT
(slot 4)
BIT
19
18-12
11 - 0
19 - 4
3-0
19 - 4
3-0
19 - 4
3-0
DESCRIPTION
Read/write control, 1 for read and 0 for write
Control register address
This field should be cleared to 0
Control register write data. It should be cleared to 0 if current
operation is read.
This field should be cleared to 0
PCM playback data for left channel
This field should be cleared to 0
PCM playback data for right channel
This field should be cleared to 0
The structure of input frame is shown as below:
Slot #
0
1
2
3
4
5 6 7 8 9 10 11 12
status status PCM PCM
Content Tag
ADDR DATA LEFT RIGHT
Unused
Bits
0-15 19-0 19-0 19-0 19-0
159 - 0
The input frame data format is shown as following:
SLOT #
BIT
DESCRIPTION
15 Frame validity bit, 1 is valid, 0 is invalid.
Tag
(slot 0)
14 - 3
Slot validity, but in W90P710, only bits 6-3 are used, bits 14-7 are
unused. Bit 3 is corresponding to slot 1, bit 4 is corresponding to slot
2, etc.. 1 is valid, 0 is invalid. The unused bits 14-7 should be cleared
to 0.
2 - 0 This field should be cleared to 0.
19 This bit should be cleared to 0
Status ADDR
(slot 1)
Status DATA
(slot 2)
18-12 Control register address echo which previous frame requested
11
10
9-0
19 - 4
3-0
PCM data for left channel request, it should be always 0 when
VRA=0 (VRA: Variable Rate Audio mode).
PCM data for right channel request (Same as Bit 11).
This field should be cleared to 0
Control register read data which previous frame requested. It should
be cleared to 0 if this slot is invalid.
This field should be cleared to 0
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Publication Release Date: January 17, 2005
Revision A.2