W90P710_05 Datasheet, PDF (335/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[7:6]
[3]
[2]
[1]
[0]
RFITL
DMS
TFR
RFR
FME
DESCRIPTIONS
RX FIFO Interrupt (Irpt_RDA) Trigger Level
RFITL [7:6] Irpt_RDA Trigger Level (Bytes)
00
01
01
04
10
08
11
14
DMA Mode Select
The DMA function is not implemented in this version.
TX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The
TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is
returned to 0 automatically after the reset pulse is generated.
RX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The
RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit
is returned to 0 automatically after the reset pulse is generated.
FIFO Mode Enable
Because UART is always operating in the FIFO mode, writing this bit has no
effect while reading always gets logical one. This bit must be 1 when other
FCR bits are written to; otherwise, they will not be programmed.
UART Line Control Register (UART_LCR)
Register
UART_LCR
Offset
0x0C
R/W Description
R/W _{Line Control Register}
Reset Value
0x0000_0000
31
23
15
7
DLAB
30
22
14
6
BCB
29
21
13
5
SPE
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
EPE
PBE
26
18
10
2
NSB
25
24
17
16
9
8
1
0
WLS
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Publication Release Date: January 17, 2005
Revision A.2