W90P710_05 Datasheet, PDF (473/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
USI_Control and Status Register (USI_CNTRL)
REGISTER ADDRESS R/W
DESCRIPTION
USI_CNTRL 0xFFF8_6200 R/W USI Control and Status Register
RESET VALUE
0x0000_0004
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
IE
IF
15
14
13
12
11
10
9
8
SLEEP
Reserved LSB
Tx_NUM
7
6
5
4
3
2
1
0
Tx_BIT_LEN
Tx_NEG Rx_NEG GO_BUSY
BITS
[31:18]
[17]
[16]
[15:12]
Reserved
IE
IF
SLEEP
DESCRIPTIONS
Reserved
Interrupt Enable
0 = Disable USI Interrupt.
1 = Enable USI Interrupt.
Interrupt Flag
0 = It indicates that the transfer dose not finish yet.
1 = It indicates that the transfer is done. The interrupt flag is set if it
was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Suspend Interval
These four bits provide the configuration of suspend interval between
two successive transmit/receive in a transfer. The default value is 0x0.
When CNTRL [Tx_NUM] = 00, setting this field has no effect on
transfer. The desired interval is obtained according to the following
equation (from the last falling edge of current sclk to the first rising
edge of next sclk):
(CNTRL[SLEEP] + 2)*period of SCLK
SLEEP = 0x0 … 2 SCLK clock cycle
SLEEP = 0x1 … 3 SCLK clock cycle
……
SLEEP = 0xe … 16 SCLK clock cycle
SLEEP = 0xf … 17 SCLK clock cycle
- 473 -
Publication Release Date: January 17, 2005
Revision A.2