W90P710_05 Datasheet, PDF (134/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[31:25]
[24]
[23]
[22]
[21]
DESCRIPTIONS
Reserved -
EnTxBErr
The Enable Transmit Bus Error Interrupt controls the TxBErr
interrupt generation. If TxBErr of MISTA register is set, and both
EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TxBErr of MISTA register is set.
1’b0: TxBErr of MISTA register is masked from Tx interrupt generation.
1’b1: TxBErr of MISTA register can participate in Tx interrupt
generation.
EnTDU
The Enable Transmit Descriptor Unavailable Interrupt controls the
TDU interrupt generation. If TDU of MISTA register is set, and both
EnTDU and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is
generated to CPU even the TDU of MISTA register is set.
1’b0: TDU of MISTA register is masked from Tx interrupt generation.
1’b1: TDU of MISTA register can participate in Tx interrupt generation.
EnLC
The Enable Late Collision Interrupt controls the LC interrupt
generation. If LC of MISTA register is set, and both EnLC and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnLC or EnTXINTR is disabled, no Tx interrupt is generated to CPU
even the LC of MISTA register is set.
1’b0: LC of MISTA register is masked from Tx interrupt generation.
1’b1: LC of MISTA register can participate in Tx interrupt generation.
EnTXABT
The Enable Transmit Abort Interrupt controls the TXABT interrupt
generation. If TXABT of MISTA register is set, and both EnTXABT and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnTXABT or EnTXINTR is disabled, no Tx interrupt is generated to
CPU even the TXABT of MISTA register is set.
1’b0: TXABT of MISTA register is masked from Tx interrupt generation.
1’b1: TXABT of MISTA register can participate in Tx interrupt
generation.
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