W90P710_05 Datasheet, PDF (20/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
5. PIN DESCRIPTION
Table 5.1 W90P710 Pins Description
PIN NAME IO TYPE
DESCRIPTION
Clock & Reset
EXTAL (15M)
I
XTAL (15M)
O
EXTAL (32768)
I
XTAL (32768)
O
nRESET
IS
JTAG Interface
TCK
IDS
TMS
IUS
TDI
IUS
TDO
O
nTRST
IUS
External Bus Interface
A [21:18]
O
A [17:0]
IOS
D [31:16] /
VD[23:8] /
IO
GPIO [67:52]
D [15:0] /
IOS
nWBE [3:0] /
SDQM [3:0] /
IOS
GPIO[69:68]
nSCS [1:0]
O
nSRAS
O
nSCAS
O
nSWE
O
MCKE
O
MCLK
O
nWAIT /
GPIO[70] /
IUS
nIRQ5
nBTCS
O
nECS [3:0]
IO
nOE
O
15MHz External Clock / Crystal Input
15MHz Crystal Output
32768Hz External Clock / Crystal Input(for RTC)
32768Hz Crystal Output(for RTC)
System Reset, active-low
JTAG Test Clock, internal pull-down with 58K ohm
JTAG Test Mode Select, internal pull-up with 70K ohm
JTAG Test Data in, internal pull-up with 70K ohm
JTAG Test Data out
JTAG Reset, active-low, internal pull-up with 70K ohm
Address Bus (MSB) of external memory and IO devices.
Address Bus of external memory and IO devices.
Data Bus (MSB) of external memory and IO device, internal pull-up with 70K
ohm.
General Programmable In/Out Port GPIO[67:52].
Data Bus (LSB) of external memory and IO device.
Write Byte Enable for specific device (nECS [3:0]).
Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.
General Programmable In/Out Port [69:68]
SDRAM chip select for two external banks, active-low.
Row Address Strobe for SDRAM, active-low.
Column Address Strobe for SDRAM, active-low.
SDRAM Write Enable, active-low
SDRAM Clock Enable, active-high
System Master Clock Out, SDRAM clock, output with slew-rate control
External Wait, active-low.
This pin indicates that the external devices need more active cycle during
access operation.
General Programmable In/Out Port GPIO[70]. If memory and IO devices in EBI
do not need wait request, it can be configured as GPIO[7] or nIRQ5
ROM/Flash Chip Select, active-low.
External I/O Chip Select, active-low.
ROM/Flash, External Memory Output Enable, active-low.
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