W90P710_05 Datasheet, PDF (163/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
7.6.2 GDMA Register Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER
ADDRESS R/W
DESCRIPTION
RESET VALUE
Channel 0
GDMA_CTL0
0xFFF0_4000 R/W Channel 0 Control Register
0x0000_0000
GDMA_SRCB0
GDMA_DSTB0
GDMA_TCNT0
GDMA_CSRC0
0xFFF0_4004
0xFFF0_4008
0xFFF0_400C
0xFFF0_4010
GDMA_CDST0 0xFFF0_4014
GDMA_CTCNT0 0xFFF0_4018
R/W Channel 0 Source Base Address Register
R/W Channel 0 Destination Base Address Register
R/W Channel 0 Transfer Count Register
R Channel 0 Current Source Address Register
R
Channel 0 Current Destination Address
Register
R Channel 0 Current Transfer Count Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Channel 1
GDMA_CTL1
0xFFF0_4020 R/W Channel 1 Control Register
0x0000_0000
GDMA_SRCB1
GDMA_DSTB1
GDMA_TCNT1
GDMA_CSRC1
0xFFF0_4024
0xFFF0_4028
0xFFF0_402C
0xFFF0_4030
GDMA_CDST1 0xFFF0_4034
GDMA_CTCNT1 0xFFF0_4038
R/W Channel 1 Source Base Address Register
R/W Channel 1 Destination Base Address Register
R/W Channel 1 Transfer Count Register
R Channel 1 Current Source Address Register
R
Channel 1 Current Destination Address
Register
R Channel 1 Current Transfer Count Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1)
REGISTER
GDMA_CTL0
GDMA_CTL1
ADDRESS
0xFFF0_4000
0xFFF0_4020
R/W
R/W
R/W
DESCRIPTION
Channel 0 Control Register
Channel 1 Control Register
RESET VALUE
0x0000_0000
0x0000_0000
31
RESERVED
23
RW_TC
15
DM
7
SAFIX
30
29
28
27
26
25
TC_WIDTH
REQ_SEL
REQ_ATV
22
21
20
19
18
17
SABNDERR DABNDERR GDMAERR AUTOIEN TC
BLOCK
14
13
12
11
10
9
RESERVED
TWS
SBMS RESERVED BME
6
5
4
3
2
1
DAFIX
SADIR
DADIR
GDMAMS
RESERVED
24
ACK_ATV
16
SOFTREQ
8
SIEN
0
GDMAEN
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Publication Release Date: January 17, 2005
Revision A.2