W90P710_05 Datasheet, PDF (247/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
SD Host interface Initial Register (SDHIIR)
REGISTER ADDRESS
SDHIIR 0xFFF0_7304
R/W
DESCRIPTION
R/W ^{SD Host Interface Initial Register}
RESET VALUE
0x0000_0018
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
SPD
7
6
5
4
3
2
1
0
SD_CLK
BITS
[31:9]
Reserved
[8]
SPD
[7:0]
SD_CLK
DESCRIPTIONS
-
Data Bus Width Control
0=1-bit data bus
1=4-bit data bus
SD Clock Control
The frequency of SD clock will be equal to (Input Clock/(SD_CLK+1)).
The SD_CLK = 8’h00 is reserved.
SD Interface Interrupt Enable Register (SDIIER)
REGISTER
SDIIER
ADDRESS
0xFFF0_7308
R/W
DESCRIPTION
R/W SD Interface Interrupt Enable Register
RESET VALUE
0x0000_0000
31
30
29
23
22
21
15
14
13
7
6
5
Reserved
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
SDIO_IEN DAT0_IEN
26
18
10
2
CD_IEN
25
17
9
1
DO_IEN
24
16
8
0
DI_IEN
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Publication Release Date: January 17, 2005
Revision A.2