W90P710_05 Datasheet, PDF (441/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
31
23
15
7
SC_RESET
30
29
22
21
14
13
RESERVED
6
TSRE
5
TBRE
28
27
RESERVED
20
19
RESERVED
12
11
4
SBD
3
NSER
26
25
18
17
10
TOF2
2
PBER
9
TOF1
1
OER
24
16
8
TOF0
0
RDR
BITS
[31:11]
RESERVED
[10:8]
TOF2,
TOF1,
TOF0
[7]
SC_RESET
[6]
TSRE
[5]
TBRE
[4]
SBD
DESCRIPTIONS
RESERVED
TOF2 is Time-Out Flag of Timer2.
When Timer 2 time out, it will set the FLAG (TOF2)
When host reads SCSR, it clears this bit to "0".
TOF1 is Time-Out Flag of Timer1.
When Timer 1 time out, it will set the FLAG (TOF1)
When host reads SCSR, it clears this bit to "0".
TOF0 is Time-Out Flag of Timer0.
When Timer 0 time out, it will set the FLAG (TOF0)
When host reads SCSR, it clears this bit to "0".
SC_RESET pin status
This bit reflects the RESET pin high or low.
Transmitter Shift Register Empty
This bit is set to "1" when transmitter shift register is empty.
Transmitter Buffer Register Empty
In non-FIFO mode, this bit will be set to a logical 1 when a data
byte is transferred from TBR to TSR. If ETBREI of IER is a logical
1, an interrupt is generated to notify host to write the following data
bytes. In FIFO mode, this bit is set to "1" when the transmitter FIFO
is empty. It is cleared to "0" when host writes data bytes into TBR
or FIFO.
Silent Byte Detected
This bit is set to "1" to indicate that received data byte are kept in
silent state for a full byte time, including start bit, data bits, parity
bit, and stop bits. In FIFO mode, it indicates the same condition for
the data on top of FIFO. When host reads SCSR, it clears this bit
to "0".
- 441 -
Publication Release Date: January 17, 2005
Revision A.2