W90P710_05 Datasheet, PDF (90/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
7.4.4 Data Cache
The W90P710 data cache (D-Cache) is a 4KB two-way set associative cache. The cache organization is
128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache is designed for buffer write-through mode of operation and a least recently used
(LRU) replacement algorithm is used to select a line when no empty lines are available.
When D-Cache is disabled, the cache memory is served as 4KB On-chip RAM.
The D-Cache is always disabled on reset.
The following is a list of the data cache features：
y 4K bytes data cache
y Two-way set associative
y Four words in a cache line
y LRU replacement policy
y Lockable on a per-line basis
y Critical word first, burst access
y Buffer Write-through mode
y 8 words write buffer
y Drain write buffer
Data Cache Operation
On a data fetch, bits 10-4 of the data’s address point into the cache to retrieve the tags and data of one
set. The tags from both ways are then compared against bits 30-11 of the data’s address. If a match is
found and the matched entry is valid, then it is a cache hit. If neither tags match nor the matched tag is
not valid, it is a cache miss.
Data Cache Read
Read Hit：On a cache hit, the requested word is immediately transferred to the core.
Read Miss：A line in the cache is selected to hold the data, which will be fetched from memory. The
selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is
selected first. If neither of the two candidate lines in the selected set is invalid, then one of the lines is
selected by the LRU algorithm to replace. The transfer begins with the aligned word containing the
missed data (critical word first), followed by the remaining word in the line, then by the word at the
beginning of the line (wraparound). As the missed word is received from the bus, it is delivered directly to
the core.
Data Cache Write
As buffer write-through mode, store operations always update memory. The buffer write-through mode is
used when external memory and internal cache images must always agree.
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