W90P710_05 Datasheet, PDF (262/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
LCD Controller is an AHB Master at AMBA and fetching video data from an AHB Slave such as SDRAM
or FLASH memory. If AHB Slave response ERROR for LCD Controller’s data request, AHBERIS will be
set.
If the data rate of output to LCD Panel is too fast and the data rate of fetch data from AMBA is too slow;
there are no data in FIFO for LCD Panel’s request, UNDRISx will be set. LCD Timing Generation register
need to be re-configured.
HSIS and VSIS provide information for firmware to know the status of LCD Panel.
VLFINISx and VFFINISx provide information for firmware to know how much data FIFO have fetched.
LCD Interrupt Clear Register (LCDINTC)
REGISTER
ADDRESS
R/W
DESCRIPTION
LCDINTC 0xFFF0_800C W LCD interrupt clear register
RESET VALUE
0x0000_0000
31
30
23
22
15
14
7
6
Reserved
29
21
Reserved
13
5
HSIC
28
27
Reserved
20
19
12
4
VSIC
11
Reserved
3
VLFINIC2
26
18
UNDRIC2
10
2
VFFINIC2
25
17
UNDRIC1
9
1
VLFINIC1
24
16
AHBERIC
8
0
VFFINIC1
BITS
[31:20]
[18]
[17]
[16]
[15:6]
[5]
[4]
Reserved
UNDRIC2
UNDRIC1
AHBERIC
Reserved
HSIC
VSIC
DESCRIPTIONS
Reserved
Clear FIFO2 UNDERRUN interrupt
Clear FIFO1 UNDERRUN interrupt
Clear MBERROR interrupt
Reserved
Clear HSYNC interrupt
Clear VSYNC interrupt
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