W90P710_05 Datasheet, PDF (242/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[31:7]
Reserved
[6]
ERRIEN
[5]
DRdIEN
[4]
DWrIEN
[3]
SDHIIEN
[0]
SDIOGIEN
DESCRIPTIONS
-
Bus Error Interrupt Enable
DMA Read Interrupt Enable
This bit controls the SDIO host controller interrupt generation from the
interrupt of the DMA read operation.
1’b0: DMA read interrupt is masked from SDIO host controller interrupt
generation
1’b1: DMA read interrupt can participate in SDIO host controller
interrupt generation
DMA Write Interrupt Enable
This bit controls the SDIO host controller interrupt generation from the
interrupt of the DMA write operation.
1’b0: DMA write interrupt is masked from SDIO host controller interrupt
generation
1’b1: DMA write interrupt can participate in SDIO host controller
interrupt generation
Secure Digital Host Controller Interface Interrupt Enable
This bit controls the SDIO host controller interrupt generation from the
interrupt of Secure Digital host controller.
1’b0: Secure Digital host controller’s interrupt is masked from SDIO
host controller interrupt generation
1’b1: Secure Digital host controller’s interrupt can participate in SDIO
host controller interrupt generation
SDIO Host Global Interrupt Enable
This bit controls the interrupt generation of SDIO host controller
Globally.
1’b0: Disable SDIO host controller interrupt generation globally
1’b1: Enable SDIO host controller interrupt generation globally
SD global Interrupt Status Register (SDGISR)
REGISTER ADDRESS
SDGISR 0xFFF0_7010
R/W
R/W
DESCRIPTION
SD Global Interrupt Status Register
RESET VALUE
0x0000_0000
- 242 -