W90P710_05 Datasheet, PDF (513/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
SDIO Control Register Map, continued
REGISTER
OFFSET
SDIER
SDISR
SDAUG
SDRSP0
SDRSP1
SDBLEN
FB0_0
…..
FB0_127
FB1_0
…..
FB1_127
0xFFF0_7308
0xFFF0_730C
0xFFF0_7310
0xFFF0_7314
0xFFF0_7318
0xFFF0_731C
0xFFF0_7400
…..
0xFFF0_75FC
0xFFF0_7800
...
0xFFF0_79FC
R/W
DESCRIPTION
R/W _{SD Interrupt Enable Register}
R/W SD Interrupt Status Register
RESET
VALUE
0x0000_0000
0x0000_00XX
R/W _{SD Command Argument Register}
0x0000_0000
R _{SD Receive Response Token Register 0} 0xXXXX_XXXX
R _{SD Receive Response Token Register 1} 0x0000_XXXX
R/W _{SD Block Length Register}
0x0000_0000
R/W Flash Buffer 0
Undefined
R/W Flash Buffer 1
Undefined
LCDC Control Register Map
REGISTER NAME
ADDRESS
LCDCON
0xFFF0_8000
LCDIMSC
0xFFF0_8004
LCDINTS
0xFFF0_8008
LCDINTC
0xFFF0_800C
OSDUPSCF
0xFFF0_8010
VDUPSCF
OSDDNSCF
0xFFF0_8014
0xFFF0_8018
VDDNSCF
0xFFF0_801C
FIFOCON
FIFOSTATUS
FIFO1PRM
FIFO2PRM
FIFO1SADDR
0xFFF0_8020
0xFFF0_8024
0xFFF0_8028
0xFFF0_802C
0xFFF0_8030
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
DESCRIPTION
RESET VALUE
LCD Controller control register
0x0000_0000
Interrupt Mask Set/Clear Register 0x0000_0000
Masked Interrupt Status Register 0x0000_0000
Interrupt Clear Register
0x0000_0000
OSD data Horizontal/Vertical up-
scaling factor
Video image Horizontal/Vertical
up-scaling factor
OSD data Horizontal/Vertical
down-scaling factor
0x0000_0000
0x0000_0000
0x0000_0000
Video image Horizontal/Vertical 0x0000_0000
down-scaling factor
LCD FIFOs control register
0x0000_0000
LCD FIFOs status
0x0000_0000
LCD FIFO1 parameters
0x0000_0000
LCD FIFO2 parameters
0x0000_0000
LCD FIFO1 transfer start address 0x0000_0000
register
- 513 -
Publication Release Date: January 17, 2005
Revision A.2