W90P710_05 Datasheet, PDF (507/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
EMC Registers Map, continued
REGISTER
CAM12M
CAM12L
CAM13M
CAM13L
CAM14M
CAM14L
CAM15M
CAM15L
TXDLSA
RXDLSA
ADDRESS
0xFFF0_3068
0xFFF0_306C
0xFFF0_3070
0xFFF0_3074
0xFFF0_3078
0xFFF0_307C
0xFFF0_3080
0xFFF0_3084
0xFFF0_3088
0xFFF0_308C
MCMDR
MIID
MIIDA
FFTCR
TSDR
RSDR
DMARFC
MIEN
MISTA
MGSTA
MPCNT
MRPC
MRPCC
MREPC
DMARFS
CTXDSA
0xFFF0_3090
0xFFF0_3094
0xFFF0_3098
0xFFF0_309C
0xFFF0_30A0
0xFFF0_30A4
0xFFF0_30A8
0xFFF0_30AC
0xFFF0_30B0
0xFFF0_30B4
0xFFF0_30B8
0xFFF0_30BC
0xFFF0_30C0
0xFFF0_30C4
0xFFF0_30C8
0xFFF0_30CC
CTXBSA
CRXDSA
0xFFF0_30D0
0xFFF0_30D4
CRXBSA 0xFFF0_30D8
R/W
DESCRIPTION
R/W CAM12 Most Significant Word Register
R/W CAM12 Least Significant Word Register
R/W CAM13 Most Significant Word Register
R/W CAM13 Least Significant Word Register
R/W CAM14 Most Significant Word Register
R/W CAM14 Least Significant Word Register
R/W CAM15 Most Significant Word Register
R/W CAM15 Least Significant Word Register
RESET VALUE
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
R/W Transmit Descriptor Link List Start Address Register 0xFFFF_FFFC
R/W Receive Descriptor Link List Start Address 0xFFFF_FFFC
Register
R/W MAC Command Register
0x0000_0000
R/W MII Management Data Register
0x0000_0000
R/W MII Management Control and Address Register 0x0090_0000
R/W FIFO Threshold Control Register
0x0000_0101
W Transmit Start Demand Register
Undefined
W Receive Start Demand Register
Undefined
R/W Maximum Receive Frame Control Register
0x0000_0800
R/W MAC Interrupt Enable Register
0x0000_0000
R/W _{MAC Interrupt Status Register}
0x0000_0000
R/W _{MAC General Status Register}
0x0000_0000
R/W _{Missed Packet Count Register}
0x0000_7FFF
R _{MAC Receive Pause Count Register}
0x0000_0000
R _{MAC Receive Pause Current Count Register} 0x0000_0000
R _{MAC Remote Pause Count Register}
0x0000_0000
R/W _{DMA Receive Frame Status Register}
0x0000_0000
R _{Current Transmit Descriptor Start Address} 0x0000_0000
Register
R Current Transmit Buffer Start Address Register 0x0000_0000
R Current Receive Descriptor Start Address 0x0000_0000
Register
R Current Receive Buffer Start Address Register 0x0000_0000
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Publication Release Date: January 17, 2005
Revision A.2