W90P710_05 Datasheet, PDF (457/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
7.17.3 Functional description
The following description uses abbreviations to refer to control/status registers and their contents of
Smart Card interface as seen in section 7.12.2
z Initialization
User needs to program control registers so that ATR (Answer To Reset) data streams can be properly
decoded after card insertion. Initialization settings include the following steps where sequential order
is irrelevant.
1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default
transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3.
2. GTR is programmed with 01h for one stop bit.
3. Set SCFR bit 1 to "1" to reset receiver FIFO.
4. Set EPE bit in SCCR bit 4 to be “1” for EVEN parity, set EPE bit to be “0” for odd parity.
5. Set SCKFS1 and SCKFS0 to "05" to select 2.5 MHz for SCCLK on 80MHz system clock.
Most default values of above control bits are designed as specified in initialization step but it is
recommended that user performs all the initialization sequence to avoid any ambiguity.
The relationship between transmission factors and settings of BLH, BLL and CBR is best described in
the following example.
1etu = ^F × ¹
Df
(f means SCCLK frequency)
Therefore,
Fd ₌ 372 _{= (BLH, BLL)× CBR = 31×12}
Dd 1
z Activation
Card insertion pulls up SCPSNT (assuming SCPSNT in ISR bit 5 is active high) and in consequence
SCPWR# is pulled down to activate power MOS to supply power to card slot after a delay of about 5
ms. This delay is for card slot mechanism to settle down before power is actually applied.
SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and
pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock
cycles to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3).
To meet another timing requirement, tc of ISO/IEC 7816-3, a counter based on SCCLK is
implemented to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR
(Answer To Reset) is detected after 65536 clock cycles from the rising edge of SCRST#.
z Answer-to-Reset
Answer-to-Reset (ATR) is the data streams sent by the card to the interface as an answer to a reset
on SCRST# signal. Refer to ISO/IEC 7816-3 for detailed description of ATR.
There're two kinds of cards specified in ISO/IEC 7816-3, inverse convention card and direct
convention card. Although these two conventions treat logical meanings (0 or 1) of voltage levels (low
or high) differently, Winbond's implementation of Smart Card interface decodes a high voltage level
data bit as "1" and low voltage level data bit "0" nevertheless and resorts to software to interpret
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Publication Release Date: January 17, 2005
Revision A.2