W90P710_05 Datasheet, PDF (339/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
DESCRIPTIONS
Parity Error Indicator
[2]
PEI
This bit is set to logic 1 whenever the received character does not have a
valid "parity bit", and is reset whenever the CPU reads the contents of the
LSR.
Overrun Error Indicator
An overrun error will occur only after the RX FIFO is full and the next
[1]
OEI
character has been completely received in the shift register. The character
in the shift register is overwritten, but it is not transferred to the RX FIFO.
OE is indicated to the CPU as soon as it happens and is reset whenever
the CPU reads the contents of the LSR.
RX FIFO Data Ready
[0]
RFDR 0 = RX FIFO is empty
1 = RX FIFO contains at least 1 received data word.
LSR [4:2] (BII, FEI, PEI) are revealed to the CPU when its associated character is at the top of the RX
FIFO. These three error indicators are reset whenever the CPU reads the contents of the LSR.
LSR [4:1] (BII, FEI, PEI, OEI) are the error conditions that produce a "receiver line status interrupt"
(Irpt_RLS) when IER [2]=1. Reading LSR clears Irpt_RLS. Writing LSR is a null operation (not
suggested)
UART Modem Status Register (UART_MSR)
REGISTER OFFSET
UART_MSR 0x18
R/W
DESCRIPTION
R MODEM Status Register (Optional)
RESET VALUE
0x0000_0000
31
23
15
7
Reserved
30
22
14
6
Reserved
29
21
13
5
DSR#
28
27
Reserved
20
19
Reserved
12
11
Reserved
4
3
Reserved Reserved
26
18
10
2
Reserved
25
17
9
1
DDSR
24
16
8
0
Reserved
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Publication Release Date: January 17, 2005
Revision A.2