W90P710_05 Datasheet, PDF (437/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Smart Card FIFO control Register (SCHI_SCFR)
REGISTER
ADDRESS
R/W
DESCRIPTION
SCHI_SCFR0 0xFFF8_5008 (DLAB = 0) W Interrupt Status Register 0
SCHI_SCFR1 0xFFF8_5808 (DLAB = 0) W Interrupt Status Register 1
RESET VALUE
0x0000_0000
0x0000_0000
31
23
15
7
RxTL1
30
22
14
6
RxTL0
29
21
13
5
PEC2
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
PEC1
3
PEC0
26
25
24
18
17
16
10
9
8
2
1
0
TxFRST RxFRST Reserved
BITS
[31:8] RESERVED -
DESCRIPTIONS
[7:6]
RxTL1,
RxTL0
Receiver FIFO active Threshold Level control bits. These two bits are
used to set the active level for the receiver FIFO interrupt. For example,
if the interrupt active level is set as 4 bytes, once there are at least 4
data characters in the receiver FIFO, an interrupt is activated to notify
host to read data from FIFO. Default to be 00b.
RxTL1
0
0
1
1
RxTL0
0
1
0
1
Rx FIFO Interrupt Active Level (Bytes)
01
04
08
14
- 437 -
Publication Release Date: January 17, 2005
Revision A.2