W90P710_05 Datasheet, PDF (359/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Timer Interrupt Status Register (TISR)
REGISTER ADDRESS R/W
DESCRIPTION
TISR
0xFFF8_1018 R/W Timer Interrupt Status Register
RESET VALUE
0x0000_0000
31
23
15
7
BITS
[1]
[0]
30
22
14
6
TIF1
TIF0
29
28
27
Reserved
21
20
19
Reserved
13
12
11
Reserved
5
4
3
Reserved
26
25
24
18
17
16
10
9
8
2
1
0
TIF1
TIF0
DESCRIPTIONS
Timer Interrupt Flag 1
This bit indicates the interrupt status of Timer channel 1.
0 = It indicates that the Timer 1 dose not countdown to zero yet.
1 = It indicates that the counter of Timer 1 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Timer Interrupt Flag 0
This bit indicates the interrupt status of Timer channel 0.
0 = It indicates that the Timer 0 dose not countdown to zero yet.
1 = It indicates that the counter of Timer 0 has decremented to zero.
The interrupt flag is set if it was enable.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Watchdog Timer Control Register (WTCR)
REGISTER ADDRESS R/W
DESCRIPTION
WTCR 0xFFF8_101C R/W Watchdog Timer Control Register
RESET VALUE
0x0000_0400
- 359 -
Publication Release Date: January 17, 2005
Revision A.2