W90P710_05 Datasheet, PDF (442/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued
BITS
[3]
NSER
[2]
PBER
[1]
OER
[0]
RDR
DESCRIPTIONS
No Stop bit Error
This bit is set to "1" to indicate that received data has no stop bit.
In FIFO mode, it indicates the same condition for the data on top of
FIFO. When host reads SCSR, it clears this bit to "0".
Parity Bit Error
This bit is set to "1" to indicate that parity bit of received data is
wrong. In FIFO mode, it indicates the same condition for the data
on top of the FIFO. When host reads SCSR, it clears this bit to "0".
Overrun Error
This bit is set to "1" to indicate previously received data is
overwritten by the next received data before it is read by host. In
FIFO mode, it indicates the same condition instead of FIFO full.
When host reads SCSR, it clears this bit to "0".
Receiver Data Ready
This bit is set to "1" to indicate received data is ready to be read by
host in RBR or FIFO. If no data are left in RBR or FIFO, the bit is
cleared to "0".
Smart Card Host Guard Time Register (SCHI_GTR)
REGISTER
SCHI_GTR0
SCHI_GTR1
ADDRESS
0xFFF8_5018
0xFFF8_5818
R/W
R/W
R/W
DESCRIPTION
Guard time Register 0
Guard time Register 1
RESET VALUE
0x0000_0001
0x0000_0001
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
GTR[7:0]
BITS
[31:8]
RESERVED
[7:0]
GTR
DESCRIPTIONS
-
Guard Time Register value.
This register specifies number of stop bits appended in the end of
data byte.
Bit 7 ~ 0: Guard time values. Default to be 01h.
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