W90P710_05 Datasheet, PDF (435/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued
BITS
[1]
ETBREI
[0]
ERDRI
DESCRIPTIONS
Enable Transmit Buffer Empty interrupt bit
An ETBREI means interrupt enable bit for TBR (Transmitter Buffer
Register) empty condition. An interrupt is issued when TBR is empty and
this bit is set to "1".
0 = TBR empty interrupt is disabled.
1 = TBR empty interrupt is enabled.
Enable Receive Data Ready interrupt bit
The active FIFO threshold level for this kind of interrupt when FIFO is
enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of SCFR at
base address + 8. Refer to description of SCFR for details). An
interrupt is issued if a data byte is ready for host to read when FIFO is
disabled or incoming data from card reaches active FIFO threshold level
when FIFO is enabled.
Interrupt Status Register (SCHI_ISR)
REGISTER
SCHI_ISR0
SCHI_ISR1
ADDRESS
R/W
DESCRIPTION
0xFFF8_5008 (DLAB = 0) R Interrupt Status Register 0
0xFFF8_5808 (DLAB = 0) R Interrupt Status Register 1
RESET VALUE
0x0000_00C1
0x0000_00C1
31
23
15
7
FIFO
enabled
30
29
22
21
14
13
6
FIFO
enabled
5
SCPSNT
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
SCPTI
INTS2
26
18
10
2
INTS1
25
24
17
16
9
8
1
INTS0
0
Interrupt
pending
This register contains mainly interrupt status including transmission-related interrupts and SCPSNT
toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART
implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR
(write only Smart Card FIFO Register at base address + 8 when BDLAB = 0) and SCPSNT line status.
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Publication Release Date: January 17, 2005
Revision A.2