W90P710_05 Datasheet, PDF (351/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
DESCRIPTIONS
[3:2] Reserved -
[1] RTS#
Complement version of RTS# (Request-To-Send) signal
Writing 0x00 to MCR, RTS# bit are set to logic 1’s;
Writing 0x0f to MCR, RTS# bit are reset to logic 0’s.
[0] Reserved -
HSUART Line Status Control Register (HSUART_LSR)
REGISTER
OFFSET R/W
HSUART_LSR 0x14
R
DESCRIPTION
Line Status Register
RESET VALUE
0x6060_6060
31
30
23
22
15
14
7
6
ERR_RX
TE
29
21
13
5
THRE
28
27
26
25
24
Reserved
20
19
18
17
16
Reserved
12
11
10
9
8
Reserved
4
3
2
1
0
BII
FEI
PEI
OEI
RFDR
BITS
[31:8]
[7]
[6]
DESCRIPTIONS
Reserved
ERR_RX
RX FIFO Error
0 = RX FIFO works normally
1 = There is at least one parity error (PE), framing error (FE), or break
indication (BI) in the FIFO. ERR_RX is cleared when CPU reads the
LSR and if there are no subsequent errors in the RX FIFO.
Transmitter Empty
TE
0 = Either Transmitter Holding Register (THR - TX FIFO) or Transmitter
Shift Register (TSR) are not empty.
1 = Both THR and TSR are empty.
- 351 -
Publication Release Date: January 17, 2005
Revision A.2