W90P710_05 Datasheet, PDF (267/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
[18]
[17]
[16]
[15:2]
[1:0]
BPP18SW
HSWP
BSWP
Reserved
FIFOEN
DESCRIPTIONS
FIFO 18bpp image swap control bit
0=Swap Disable
1=Swap Enable
FIFO half-word swap control bit.
0 = Swap Disable
1 = Swap Enable
FIFO byte swap control bit.
0 = Swap Disable
1 = Swap Enable
Reserved
FIFOs transfer data enable
x1 = FIFO1 transfer enable x0=FIFO1 transfer disable
1x = FIFO2 transfer enable 0x=FIFO2 transfer disable
LCD FIFO Status Register (FIFOSTATUS)
REGISTER
ADDRESS
R/W
DESCRIPTION
FIFOSTATUS 0xFFF0_8024 R LCD FIFOs status register
RESET VALUE
0x0000_0000
31
30
23
22
15
14
7
6
29
28
27
26
Reserved
21
20
19
18
Reserved
13
12
11
10
Reserved
5
4
3
2
Reserved
BITS
[31:2]
[1:0]
Reserved
MASTERID
DESCRIPTIONS
Reserved
Currently, the data bus master
01 = FIFO1 grant the bus
11 = FIFO2 grant the bus
25
24
17
16
9
8
1
0
MASTERID
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Publication Release Date: January 17, 2005
Revision A.2