W90P710_05 Datasheet, PDF (139/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
[0]
DESCRIPTIONS
EnRXINTR
The Enable Receive Interrupt controls the Rx interrupt generation.
If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC
generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx
interrupt is generated to CPU even the status bits 1~14 of MISTA are
set and the corresponding bits of MIEN are enabled. In other words, if
S/W wants to receive Rx interrupt from EMC, this bit must be enabled.
And, if S/W doesn’t want to receive any Rx interrupt from EMC,
disables this bit.
1’b0: RXINTR of MISTA register is masked and Rx interrupt generation
is disabled.
1’b1: RXINTR of MISTA register is unmasked and Rx interrupt
generation is enabled.
MAC Interrupt Status Register (MISTA)
The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO
status and also NATA processing status. The statuses kept in MISTA will trigger the reception or
transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the
status and also clears the interrupt.
REGISTER
ADDRESS R/W
DESCRIPTION
MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register
RESET VALUE
0x0000_0000
31
23
TDU
15
Reserved
7
MMP
30
22
LC
14
CFR
6
RP
29
28
Reserved
21
20
TXABT NCS
13
12
Reserved
5
4
ALIE
RXGD
27
19
EXDEF
11
RxBErr
3
PTLE
26
18
TXCP
10
RDU
2
RXOV
25
17
TXEMP
9
DENI
1
CRCE
24
TxBErr
16
TXINTR
8
DFOI
0
RXINTR
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Publication Release Date: January 17, 2005
Revision A.2