W90P710_05 Datasheet, PDF (6/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
1. GENERAL DESCRIPTION
The W90P710 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which
designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte D-
cache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static
design is particularly suitable for cost sensitive and power sensitive applications.
One 10/100 Mb MAC of Ethernet controller is built-in to reduce total system cost. A LCD controller is
also built-in to support TFT and low cost STN LCD modules.
With one USB 1.1 host controller, one USB 1.1 device controller, two smart card host controller, four
independent UARTs, one Watchdog timer, up to 71 programmable I/O ports, PS/2 keyboard controller
and an advanced interrupt controller, the W90P710 is particularly suitable for point-of-sale (POS),
access control and data collector.
The W90P710 also provides one AC97/I²S controller, one SD/SDIO host controller, one 2-Channel
GDMA, two 24-bit timers with 8-bit pre-scale, The external bus interface (EBI) controller provides for
SDRAM, ROM/SRAM, flash memory and I/O devices. The System Manager includes an internal 32-bit
system bus arbiter and a PLL clock controller. With a wide range of serial communication and
Ethernet interfaces, the W90P710 is also suitable for communication gateways as well as many other
general purpose applications.
2. FEATURES
Architecture
y Fully 16/32-bit RISC architecture
y Little/Big-Endian mode supported
y Efficient and powerful ARM7TDMI core
y Cost-effective JTAG-based debug solution
External Bus Interface
y 8/16/32-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
y Support for SDRAM
y Programmable access cycle (0-7 wait cycle)
y Four-word depth write buffer for SDRAM write data
y Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
y Two-way, Set-associative, 4K-byte I-cache and 4K-byte D-cache
y Support for LRU (Least Recently Used) Protocol
y Cache can be configured as internal SRAM
y Support Cache Lock function
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