W90P710_05 Datasheet, PDF (454/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Smart Card Host Buffer Time-Out Data Register (SCHI_BTOR)
Register
Address
R/W Description
SCHI_BTOR0 0XFFF8_5044 ^R/W Buffer Time out Data Register 0
SCHI_BTOR1 0XFFF8_5844 ^R/W Buffer Time out Data Register 1
Reset Value
0x0000_0000
0x0000_0000
31
23
15
7
BTOIE
30
22
14
6
BTOIC_6
29
21
13
5
BTOIC_5
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
BTOIC_4 BTOIC_3
26
18
10
2
BTOIC_2
25
24
17
16
9
8
1
0
BTOIC_1 BTOIC_0
BITS
[31:8]
RESERVED
[7]
BTOIE
[6:0]
BTOIC
DESCRIPTIONS
-
Buffer Time Out Interrupt Enable
The feature of receiver buffer time out interrupt is enabled only
when BTOIE[7] = ERDRI =1 .
Buffer Time Out Interrupt Comparator
The time out counter resets and starts counting (the counting clock
= ETU) whenever the RX FIFO receives a new data word. Once
the content of time out counter (TOUT_CNT) is equal to that of
time out interrupt comparator (TOIC), a receiver time out interrupt
(Irpt_TOUT) is generated if TOR[7] = ERDRI =1. A new incoming
data word or BRX FIFO empty clear Irpt_TOUT.
Smart Card Host Baud Rate Divider Latch Lower Byte (SCHI_BLL)
REGISTER
SCHI_BLL0
SCHI_BLL1
ADDRESS
0XFFF8_5000
(DLAB = 1)
0XFFF8_5800
(DLAB = 1)
R/W
DESCRIPTION
RESET
VALUE
R/W _{Baud rate divisor Latch Lower byte Register 0 0x0000_001F}
R/W _{Baud rate divisor Latch Lower byte Register 1 0x0000_001F}
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