W90P710_05 Datasheet, PDF (88/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
7.4.3 Instruction Cache
The Instruction cache (I-cache) is a 4K bytes two-way set associative cache. The cache organization is
128 sets, two lines per set, and four words per line. Cache lines are aligned on 4-word boundaries in
memory. The cache access cycle begins with an instruction request from the instruction unit in the core.
In the case of a cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the
cache initiates a burst read cycle on the internal bus with the address of the requested instruction. The
first word received from the bus is the requested instruction. The cache forwards this instruction to the
instruction unit of the core as soon as it is received from the internal bus. A cache line is then selected to
receive the data that will be coming from the bus. A least recently used (LRU) replacement algorithm is
used to select a line when no empty lines are available. When I-Cache is disabled, the cache memory is
served as 4KB On-chip RAM. The I-Cache is always disabled on reset.
The following is a list of the instruction cache features：
y 4K bytes instruction cache
y Two-way set associative
y Four words in a cache line
y LRU replacement policy
y Lockable on a per-line basis
y Critical word first, burst access
Instruction Cache Operation
On an instruction fetch, bits 10-4 of the instruction’s address point into the cache to retrieve the tags and
data of one set. The tags from both ways are then compared against bits 30-11 of the instruction’s
address. If a match is found and the matched entry is valid, then it is a cache hit. If neither tags match nor
the matched tag is not valid, it is a cache miss.
Instruction Cache Hit
In case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line
whose tag matches. The instruction is immediately transferred to the instruction unit of the core.
Instruction Cache Miss
On an instruction cache miss, the address of the missed instruction is driven on the internal bus with a 4-
word burst transfer read request. A cache line is then selected to receive the data that will be coming
from the bus. The selection algorithm gives first priority to invalid lines. If neither of the two lines in the
selected set is invalid, then the least recently used line is selected for replacement. Locked lines are
never replaced. The transfer begins with the word requested by the instruction unit (critical word first),
followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound).
Instruction Cache Flushing
The W90P710 does not support external memory snooping. Therefore, if self-modifying code is written,
the instructions in the I-Cache may become invalid. The entire I-Cache can be flushed by software in one
operation, or can be flushed one line at a time by setting the CAHCON register bit FLHS or FLHA with
the ICAH bit is set. As flushing the cache line, the “V” bit of the line is cleared to “0”. The I-Cache is
automatically flushed during reset.
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