W90P710_05 Datasheet, PDF (96/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Cache Test Register 0 (CTEST0)
Cache test control register that configures the cache and tag ram testing enable or disable. In addition,
this register controls the built-in-self-test (BIST) function of SRAM.
REGISTER
CTEST0
ADDRESS
0xFFF6_0000
R/W
DESCRIPTION
R/W Cache test register 0
RESET VALUE
0x0000_0000
31
23
15
BISTEN
7
30
29
28
27
26
25
24
RESERVED
22
21
20
19
18
17
16
RESERVED
14
13
12
11
10
9
8
RESERVED
BST_GP3 BST_GP2 BST_GP1 BST_GP0
6
5
4
3
2
1
0
RESERVED
CATEST
BITS
DESCRIPTION
[31:16]
RESERVED
-
BIST mode enable
[15]
BISTEN
When set to “1”, BIST mode will be enabled, the selected memory
groups begins to be tested by BIST.
[14:12]
RESERVED
-
Memory group 3 is selected to test by BIST
[11]
BIST_GP3
When set to “1”, memory group 3, including data cache tag ram
way 0 and way 1, are selected to be tested by BIST.
Memory group 2 is selected to test by BIST
[10]
BIST_GP2
When set to “1”, memory group 2, including program cache tag
ram way 0 and way 1, are selected to be tested by BIST.
Memory group 1 is selected to test by BIST
[9]
BIST_GP1
When set to “1”, memory group 1, including data cache ram way 0
and way 1, are selected to be tested by BIST.
Memory group 0 is selected to test by BIST
[8]
BIST_GP0
When set to “1”, memory group 0, including program cache ram
way 0 and way 1, are selected to be tested by BIST.
[7:0]
RESERVED
-
** Note: The 4 memory groups can be selected and tested simultaneously by BIST.
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