W90P710_05 Datasheet, PDF (60/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
IIS Clock Control Register (I2SCKCON)
REGISTER ADDRESS
I2SCKCON _{0xFFF0_0014}
R/W
R/W
DESCRIPTION
I2S PLL clock Control Register
RESET VALUE
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
RESERVED
7
6
5
4
3
2
PRESCALE
9
8
IISPLLEN
1
0
BITS
[31:9]
[8]
[7:0]
RESERVED
I2SPLLEN
PRESCALE
DESCRIPTION
-
IIS PLL clock source enable
Set this bit will enable PLL1 clock output to audio I2S clock input.
1 = Enable PLL1 clock source for audio I2S
0 = Disable PLL1 clock source for audio I2S
The PLL1 is shared with LCD controller, if both the LCD and I2S are
used the PLL at the same time, software can using this prescaler to
generate an appropriate clock nearly 12.288M or 16.934M. The
clock is generated as below, and if PRESCALE =0, the
PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO =
PLL_FOUT/(PRESCALE +1)”
IRQ Wakeup Control Register (IRQWAKECON)
REGISTER
ADDRESS
IRQWAKECON _{0xFFF0_0020}
R/W
R/W
DESCRIPTION
IRQ Wakeup Control Register
RESET VALUE
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
IRQWAKEUPPOL
IRQWAKEUPEN
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