W90P710_05 Datasheet, PDF (179/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Continued.
BITS
[1]
[0]
WDH
SCHO
DESCRIPTION
WritebackDoneHead
Set after the Host Controller has written HcDoneHead to
HccaDoneHead.
SchedulingOverrun
Set when the List Processor determines a Schedule Overrun has
occurred.
Host Controller Interrupt Enable Register
Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit
unchanged.
REGISTER
ADDRESS R/W
DESCRIPTION
RESET
VALUE
HcInterruptEnable 0xFFF0_5010 R/W Host Controller Interrupt Enable Register 0x0000_0000
31
30
MIE
OCE
23
22
15
14
7
6
Reserved RHCE
29
21
13
5
FNOE
28
27
26
Reserved
20
19
18
Reserved
12
11
10
Reserved
4
3
2
UREE
RDTE
SOFE
25
17
9
1
WDHE
24
16
8
0
SCHOE
BITS
[31]
[30]
[29:7]
[6]
MIE
OCE
Reserved
RHSCE
DESCRIPTION
MasterInterruptEnable
This bit is a global interrupt enable. A write of ‘1’ allows interrupts to
be enabled via the specific enable bits listed above.
OwnershipChangeEnable
0: Ignore
1: Enable interrupt generation due to Ownership Change.
Reserved. Read/Write 0's
RootHubStatusChangeEnable
0: Ignore
1: Enable interrupt generation due to Root Hub Status Change.
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Publication Release Date: January 17, 2005
Revision A.2