W90P710_05 Datasheet, PDF (53/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
PLL Control Register0 （PLLCON0）
W90P710 provides two clock generation options – crystal and oscillator. The external clock via
EXTAL(15M) Minput pin as the reference clock input of PLL module. The external clock can bypass the
PLL and be used to the internal system clock by pull-down the data D15 pin. Using PLL’s output clock
for the internal system clock, D15 pin must be pull-up.
REGISTER
PLLCON
ADDRESS
0xFFF0_0008
R/W
DESCRIPTION
R/W
PLL Control Register
RESET VALUE
0x0000_2F01
31
23
15
7
FBDV
30
29
22
21
14
13
6
5
OTDV
28
27
RESERVED
20
19
RESERVED
12
11
FBDV
4
3
26
18
10
2
INDV
25
24
17
16
PWDEN
9
8
1
0
BITS
[31:17]
[16]
[15:7]
[6:5]
[4:0]
RESERVED
PWDEN
FBDV
OTDV
INDV
DESCRIPTION
-
Power down mode enable
0 = PLL is in normal mode (default)
1 = PLL is in power down mode
PLL VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL.
PLL output clock divider
OTDV [6:5]
0
0
0
1
1
0
1
1
DIVIDED BY
1
2
2
4
PLL input clock divider
Input divider divides the input reference clock into the PLL.
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Publication Release Date: January 17, 2005
Revision A.2