W90P710_05 Datasheet, PDF (41/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
Table7.2.4 Word access read operation with Big Endian
ACCESS OPERATION
READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD WIDTH
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
XA
WORD
31 0
ABCD
WA
31 0
ABCD
31 0
ABCD
WA
HALF WORD
31 0
CDAB
WA
31 0
CD AB
31 0
CD XX
31 0
CD AB
WA
WA+2
31 0
DXXX
WA
BYTE
31 0
DCBA
WA
31 0
DCBA
31 0 31 0
DCXX DCBX
WA+1
WA+2
31 0
DCBA
WA+3
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
AAAA
31 0
ABCD
31 0
ABCD
XXAA
15 0
CD
15 0
CD
1st read
XXAA
15 0
AB
15 0
AB
2nd read
XXXA
70
D
70
D
1st read
XXXA
70
C
70
C
2nd read
XXXA
70
B
70
B
3rd read
XXXA
70
A
70
A
4th read
Table 7.2.5 and Table 7.2.6
Using big-endian and half-word access, Program/Data path between register and external memory.
HA = Address whose LSB is 0,2,4,6,8,A,C,E HAL = Address whose LSB is 0,4,8,C
HAU = Address whose LSB is 2,6,A,E
X = Don’t care
nWBE [3-0] / SDQM [3-0] = A means active and U means inactive
Table7.2.5 Half-word access write operation with Big Endian
ACCESS OPERATION
WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD WIDTH
WORD
HALF WORD
BYTE
Bit Number
CPU Reg Data
SA
Bit Number
SD
Bit Number
ED
31 0
ABCD
HAL
HAU
31 0
CD CD
31 0
CD CD
31 0
CD CD
31 0
CD CD
31 0
ABCD
HA
31 0
CD CD
31 0
CD CD
31 0
ABCD
HA
31 0
CD CD
70
C
31 0
CD CD
70
D
XA
HAL
HAL
HA
HA
HA+1
nWBE [3-0] /
SDQM [3-0]
Bit Number
XD
Bit Number
Ext. Mem Data
Timing Sequence
AAUU
31 0
CD CD
31 16
CD
UUAA
31 0
CD CD
15 0
CD
XXAA
15 0
CD
15 0
CD
XXXA
70
C
70
C
1st write
XXXA
70
D
70
D
2nd write
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Publication Release Date: January 17, 2005
Revision A.2