W90P710_05 Datasheet, PDF (375/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted
interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred.
BITS
[31:2]
[1]
[0]
Reserved
IRQ
FIQ
DESCRIPTIONS
Reserved
IRQ [1]: Interrupt Request
0 = nIRQ line is inactive.
1 = nIRQ line is active.
FIQ [0]: Fast Interrupt Request
0 = nFIQ line is inactive.
1 = nFIQ line is active
AIC Mask Enable Command Register (AIC_MECR)
REGISTER ADDRESS R/W
DESCRIPTION
AIC_MECR 0xFFF8_2120 ^W Mask Enable Command Register
RESET VALUE
Undefined
31
MEC31
23
MEC23
15
MEC15
7
MEC7
30
MEC30
22
MEC22
14
MEC14
6
MEC6
29
MEC29
21
MEC21
13
MEC13
5
MEC5
28
MEC28
20
MEC20
12
MEC12
4
MEC4
27
MEC27
19
MEC19
11
MEC11
3
MEC3
26
MEC26
18
MEC18
10
MEC10
2
MEC2
25
24
MEC25 MEC24
17
16
MEC17 MEC16
9
8
MEC9
MEC8
1
0
MEC1 RESERVED
BITS
[31:1]
[0]
MEC x
Reserved
DESCRIPTIONS
MEC x: Mask Enable Command
0 = No effect
1 = Enables the corresponding interrupt channel
Reserved
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Publication Release Date: January 17, 2005
Revision A.2