W90P710_05 Datasheet, PDF (465/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[31:12]
[11]
[10]
[9]
[8]
[5:4]
[3]
[2]
[1]
[0]
Reserved
I2C_RxAC
K
I2C_BUSY
I2C_AL
I2C_TIP
Tx_NUM
Reserved
IF
IE
I2C_EN
DESCRIPTIONS
Reserved
Received Acknowledge From Slave (Read only)
This flag represents acknowledge from the addressed slave.
0 = Acknowledge received (ACK).
1 = Not acknowledge received (NACK).
I²C Bus Busy (Read only)
0 = After STOP signal detected.
1 = After START signal detected.
Arbitration Lost (Read only)
This bit is set when the I²C core lost arbitration. Arbitration is lost when:
A STOP signal is detected, but no requested.
The master drives SDA high, but SDA is low.
Transfer In Progress (Read only)
0 = Transfer complete.
1 = Transferring data.
NOTE: When a transfer is in progress, you will not allow writing to any
register of the I²C master core except SWR.
Transmit Byte Counts
These two bits represent how many bytes are remained to transmit. When
a byte has been transmitted, the Tx_NUM will decrease 1 until all bytes are
transmitted (Tx_NUM = 0x0) or NACK received from slave. Then the
interrupt signal will assert if IE was set.
0x0 = Only one byte is left for transmission.
0x1 = Two bytes are left to for transmission.
0x2 = Three bytes are left for transmission.
0x3 = Four bytes are left for transmission.
Reserved
Interrupt Flag
The Interrupt Flag is set when:
Transfer has been completed.
Transfer has not been completed, but slave responded NACK (in multi-byte
transmit mode).
Arbitration is lost.
NOTE: This bit is read only, but can be cleared by writing 1 to this bit.
Interrupt Enable
0 = Disable I²C Interrupt.
1 = Enable I²C Interrupt.
I²C Core Enable
0 = Disable I²C core, serial bus outputs are controlled by SDW/SCW.
1 = Enable I²C core, serial bus outputs are controlled by I²C core.
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Publication Release Date: January 17, 2005
Revision A.2