W90P710_05 Datasheet, PDF (336/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
BITS
[7]
[6]
[5]
[4]
[3]
[2]
[1:0]
DESCRIPTIONS
DLAB
Divider Latch Access Bit
0 = It is used to access RBR, THR or IER.
1 = It is used to access Divisor Latch Registers {DLL, DLM}
BCB
Break Control Bit
When this bit is set to logic 1, the serial data output (SOUT) is forced to the Spacing
State (logic 0). This bit acts only on SOUT and has no effect on the transmitter logic.
Stick Parity Enable
0 = Disable stick parity
SPE _{1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as}
a logic 0 if bit 4 is 1 (even parity). This bit has effect only when bit 3 (parity bit
enable) is set.
Even Parity Enable
0 = Odd number of logic 1’s are transmitted or checked in the data word and
parity bits.
EPE
1 = Even number of logic 1’s are transmitted or checked in the data word and
parity bits.
This bit has effect only when bit 3 (parity bit enable) is set.
PBE
Parity Bit Enable
0 = Parity bit is not generated (transmit data) or checked (receive data) during
transfer.
1 = Parity bit is generated or checked between the "last data word bit" and "stop bit"
of the serial data.
NSB
Number of “STOP bit”
0= One “ STOP bit” is generated in the transmitted data
1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word
length is selected;
Two “ STOP bit” is generated when 6-, 7- and 8-bit word length is selected.
Word Length Select
WLS[1:0]
Character length
00
WLS
01
10
11
5 bits
6 bits
7 bits
8 bits
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