W90P710_05 Datasheet, PDF (508/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
EMC Registers Map, continued
REGISTER ADDRESS
RXFSM
0xFFF0_3200
TXFSM
0xFFF0_3204
FSM0
0xFFF0_3208
FSM1
0xFFF0_320C
DCR
0xFFF0_3210
DMMIR
0xFFF0_3214
BISTR
0xFFF0_3300
R/W
DESCRIPTION
R _{Receive Finite State Machine Register}
R _{Transmit Finite State Machine Register}
R _{Finite State Machine Register 0}
R _{Finite State Machine Register 1}
R/W _{Debug Configuration Register}
R _{Debug Mode MAC Information Register}
R/W BIST Mode Register
RESET VALUE
0x0081_1101
0x0101_1101
0x0001_0101
0x1100_0100
0x0000_003F
0x0000_0000
0x0000_0000
GDMA Registers Map
REGISTER
ADDRESS R/W
DESCRIPTION
RESET VALUE
GDMA_CTL0 0xFFF0_4000 R/W Channel 0 Control Register
0x0000_0000
GDMA_SRCB0 0xFFF0_4004 R/W Channel 0 Source Base Address Register
0x0000_0000
GDMA_DSTB0 0xFFF0_4008 R/W Channel 0 Destination Base Address Register 0x0000_0000
GDMA_TCNT0 0xFFF0_400C R/W Channel 0 Transfer Count Register
0x0000_0000
GDMA_CSRC0 0xFFF0_4010 R Channel 0 Current Source Address Register 0x0000_0000
GDMA_CDST0
GDMA_CTCNT
0
GDMA_CTL1
0xFFF0_4014
0xFFF0_4018
0xFFF0_4020
R
R
R/W
Channel 0 Current Destination Address Register
Channel 0 Current Transfer Count Register
Channel 1 Control Register
0x0000_0000
0x0000_0000
0x0000_0000
GDMA_SRCB1 0xFFF0_4024 R/W Channel 1 Source Base Address Register
0x0000_0000
GDMA_DSTB1 0xFFF0_4028 R/W Channel 1 Destination Base Address Register 0x0000_0000
GDMA_TCNT1 0xFFF0_402C R/W Channel 1 Transfer Count Register
0x0000_0000
GDMA_CSRC1 0xFFF0_4030 R Channel 1 Current Source Address Register 0x0000_0000
GDMA_CDST1 0xFFF0_4034 R Channel 1 Current Destination Address Register
GDMA_CTCNT
1
0xFFF0_4038
R
Channel 1 Current Transfer Count Register
0x0000_0000
0x0000_0000
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