W90P710_05 Datasheet, PDF (58/526 Pages) Winbond – 16/32-bit ARM microcontroller

W90P710
PLL Control Register 1（PLLCON1）
W90P710 provides extra PLL for LCD controller programmable pixel clock and provide 12.288/16.934
MHz clock source to Audio Controller. It uses the same 15MHz crystal clock input source with system
PLL mentioned above.
REGISTER ADDRESS
PLLCON1 _{0xFFF0_0010}
R/W
R/W
DESCRIPTION
PLL Control Register 1
31
23
15
7
FBDV1
30
29
22
21
14
13
6
5
OTDV1
28
27
RESERVED
20
19
RESERVED
12
11
FBDV1
4
3
26
18
10
2
INDV1
RESET VALUE
0x0001_0000
25
24
17
16
PWDEN1
9
8
1
0
BITS
[31:17]
[16]
[15:7]
[6:5]
[4:0]
RESERVED
PWDEN1
FBDV1
OTDV1
INDV1
DESCRIPTION
-
PLL1 power down enable
0 = PLL1 is in normal mode
1 = PLL1 is in power down mode (default)
PLL1 VCO output clock feedback divider
Feedback Divider divides the output clock from VCO of PLL1.
PLL1 output clock divider
OTDV1 [6:5]
Divided by
0
0
1
0
1
2
1
0
2
1
1
4
PLL1 input clock divider
Input divider divides the input reference clock into the PLL1.
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